1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) process, and more particularly, to a process for manufacturing a dynamic random access memory device with buried trench capacitors.
2. Description of the Prior Art
Dynamic random access memory (DRAM) is a type of volatile memory having a signal which is stored in a digital state depending on the charging state of the capacitor in each memory cell. A DRAM memory unit comprises an access transistor and a storage capacitor. The source terminal of the access transistor is connected to the storage electrode, known as the upper electrode, of a storage capacitor. The lower electrode of the storage capacitor is connected to a fixed voltage source. Between the upper electrode and the lower electrode is a dielectric thin film.
A capacitor is at the xe2x80x9cheartxe2x80x9d of a DRAM storage device. When the amount of electric charges capable of being stored in the capacitor is large, soft errors produced by a particles can be greatly lowered. Furthermore, a large charge storage capacity in the DRAM capacitor is able to lower its refreshing frequency. When a small charge storage capacity is needed in a DRAM capacitor, a conventional two-dimensional or planar type of capacitor can be fabricated in the integrated circuit. However, a planar type capacitor occupies a rather large surface area on the semiconductor substrate surface, hence is not suitable for high integration. Therefore, three-dimensional capacitors, for example, the so-called stacked type or trench type capacitors, are used for increasing the level of integration of DRAMs.
FIGS. 1A through 1L are schematic cross-sectional views showing the progression of manufacturing steps in the fabrication of an array of trench-type DRAM cells according to a conventional method. As shown in FIG. 1A and FIG. 2A, wherein FIG. 2A is a top view for illustrating the following steps and FIG. 1A is a cross-sectional view along line Ixe2x80x94I of FIG. 2A, a pad oxide layer 101 and a silicon nitride layer 102 are sequentially formed on a P type silicon substrate 100. Then, a plurality of rows of trenches 103 are formed in the P type silicon substrate 100 by patterning the silicon nitride layer 102 and the pad oxide layer 101 with a conventional photolithography and etching method. As shown in FIG. 2A, the silicon nitride layer 102 and the pad oxide layer 101 are patterned in the way such that each pair of neighboring trenches 103 in each row of the trenches 103 is separated from each other for a predetermined distance.
Referring next to FIG. 1B, a conformal silicon nitride layer 104 is deposited on the P type silicon substrate 100, and then a sacrificial layer 105 is formed on the conformal silicon nitride layer 104. Referring to FIG. 1C, the sacrificial layer 105 is partially etched away such that the depth of the left sacrificial layer 105 is under the surface of the pad oxide layer 101, and a portion of the conformal silicon nitride layer 104 in the trench 103 is exposed. Then, referring to FIG. 1D, the portion of the conformal silicon nitride layer 104 uncovered by the left sacrificial layer 105 is etched away. Afterward, the left sacrificial layer 105 is removed.
Referring to FIG. 1E, a collar oxide layer 106 is then formed around inner sidewalls of each trench 103 uncovered by the left conformal silicon nitride layer 104 by thermal oxidation. Thereafter, the left conformal silicon nitride layer 104 is removed with hot H3PO4 aqueous solution. Subsequently, referring to FIG. 1F, an N type diffusion region 107 is formed around the surrounding of each trench 103 in the silicon substrate 100, using thermal diffusion with N type impurity gas to dope the silicon substrate 100. The N type diffusion region 107 is used as a bottom electrode of the buried trench capacitor. The regions of the silicon substrate 100 covered by the collar oxide layer 106 are not doped.
Referring next to FIG. 1G, a silicon nitride/silicon dioxide (NO) composite layer 108 is formed around the inner peripheral area of each trench 103 uncovered by the collar oxide layer 106 for serving as a dielectric layer of a buried trench capacitor which will be formed later. Referring to FIG. 1H, depositing an N type doped polysilicon layer 109 on the silicon substrate 100 to fill each trench 103 and serve as the top electrode of the buried trench capacitor. The N type doped polysilicon layer 109 is partially etched to expose a part of the collar oxide layer 106 in the trench 103. Referring to FIG. 11, etching the exposed part of the collar oxide layer 106 until the surface of the N type doped polysilicon layer 109.
Referring to FIG. 1J, subsequently, depositing an amorphous silicon layer on the silicon substrate 100, and partially etching the amorphous silicon layer so that the left amorphous silicon layer forms a buried silicon strap 110 in the trench 103. The buried silicon strap 110 is then doped with N type dopants by ion implantation. An annealing step is performed so that the impanted N type dopants in the buried silicon strap 110 are out diffused to the silicon substrate 100. The N type doped buried silicon strap 110 electrically couples the top electrode of the buried trench capacitor and a source/drain region of an access transistor on the silicon substrate 100, which will be formed later. In accordance with the above steps, the buried trench capacitors are completed.
Referring to FIGS. 1K and 2B, wherein FIG. 2B is a top view for illustrating the following steps and FIG. 1K is a cross-sectional view along line IIxe2x80x94II of FIG. 2B, defining active areas for source/drain regions of the access transistors of the DRAM cells using an island type pattern 111. As a result, a trench isolation region 112 is formed in the silicon substrate 100, passing through the respective buried silicon strap 110 and a part of the respective buried trench capacitor, and between the pair of neighboring buried trench capacitors.
Referring to FIGS. 1L and 2C, wherein FIG. 2C is a top view for illustrating the following steps and FIG. 1L is a cross-sectional view along line IIIxe2x80x94III of FIG. 2, an oxide layer is deposited on the silicon substrate 100 to fill the trench isolation region 112, and then planarized by a chemical mechanical polishing process. At the chemical mechanical polishing process, the silicon nitride layer 102 and the pad oxide layer 101 are removed. Thereafter, an N well is formed in the silicon substrate 100 by ion implantation. The N well electrically couples the bottom electrode of the buried trench capacitor formed of the N type diffusion region 107 to a positive voltage bias. A gate oxide layer 114 is formed on the silicon substrate 100 by thermal oxidation. Then, a gate layer 115 serving as word lines of the DRAM cells are formed by depositing and patterning an N type doped polysilicon layer and a tungsten silicide layer. Then, the source/drain regions 116 of the access transistors are formed by ion implantation. As a consequence, the trench type DRAM cells are completed.
However, in accordance with the conventional process of manufacturing the trench type DRAM cells, the trench capacitor becomes a major limited factor in device scaling. To keep capacitance unchanged, the trench of the trench capacitor must be etched deeper to compensate capacitor area loss from horizontal scaling. It becomes very difficult and costly to etch the trench as the aspect ratio of the trench increases larger. On the other hand, because the trench capacitor is formed before other devices, increasing unit capacitance by reducing the effective dielectric thickness of the trench capacitor seems to be very difficult due to limited high dielectric materials that can sustain high temperature are available.
Accordingly, it is a need to provide an improved process for manufacturing a trench type DRAM cell, which can increase capacitance of the trench capacitor without the drawbacks of the conventional process.
It is an objective of the present invention to provide a method for forming an array of DRAM cells with buried trench capacitors, which can increase capacitance of the buried trench capacitor without either deepening the depth of the buried trench capacitor or thinning down the effective insulator""s thickness of the buried trench capacitor.
It is another objective of the present invention to provide a method for forming an array of DRAM cells with buried trench capacitors, which utilizes a strip type pattern along the pattern of the buried trench capacitors, instead of the island pattern used in a conventional DRAM process, to define active areas for source/drain regions of access transistors over the buried trench capacitors on a semiconductor substrate, such that the process window of the strip type pattern can be greatly improved.
It is a further objective of the present invention to provide a method for forming an array of DRAM cells with buried trench capacitors, which utilizes a strip type pattern along the pattern of the buried trench capacitors, instead of the island pattern used in a conventional DRAM process, to define active areas for source/drain regions of access transistors over the buried trench capacitors on a semiconductor substrate, so that overall contact resistance of a buried conductive strap which electrically couples the top electrode of the buried trench capacitor and a source/drain region of the access transistor can be reduced and properly controlled.
In order to achieve the above objectives, the present invention provides a method for forming an array of DRAM cells with buried trench capacitors. The present method begins with providing a semiconductor substrate with a first conductivity. A first dielectric layer is formed on the semiconductor substrate. The first dielectric layer then is patterned to form a plurality of rows of buried trenches in the semiconductor substrate. Each row of the buried trenches comprises a plurality of pairs of neighboring buried trenches, and each pair of the neighboring buried trenches separates from each other for a predetermined distance. A conformal dielectric layer is formed on the buried trenches. Then, a sacrificial layer is formed on the conformal dielectric layer. A portion of the sacrificial layer is removed in order that the depth of the sacrificial layer is below the surface of the first dielectric layer. The portion of the conformal dielectric layer uncovered by the sacrificial layer is removed. Then, the left portion of the sacrificial layer is removed. A collar oxide layer is formed on inner sidewalls of the buried trenches uncovered by the left portions of the conformal dielectric layer. The left portions of the conformal dielectric layer then is removed. A diffusion region with a second conductivity opposite to the first conductivity is formed around the surrounding of each buried trench in the semiconductor substrate except for the portion of the semiconductor substrate covered by the collar oxide layer. The diffusion region is served as a first electrode of a buried trench capacitor. Following, removing the portions of the collar oxide layer around the inner sidewalls of the buried trenches neighboring with each other by a photolithography and etching process. Forming a second dielectric layer on the inner peripheral area of each buried trench uncovered by the collar oxide layer by steps of including oxidation such that an inversion layer is induced on the interface between the second dielectric layer and the semiconductor substrate. The second dielectric layer is served for an insulating layer of the buried trench capacitor. A conductive layer with the second conductivity is formed on the semiconductor substrate to fill each buried trench. The conductive layer is served as a second electrode of the buried trench capacitor. Removing the conductive layer until a portion of the collar oxide layer is exposed. Then, the exposed portion of the collar oxide layer is removed. A buried conductive strap with the second conductivity is formed on the first conductive layer within each buried trench. Defining a plurality of active area on the semiconductor substrate along the rows of the buried trenches using a strip type pattern. Then, an oxide layer is formed on the semiconductor substrate to fill the buried trenches. Planarizing the oxide layer to form a trench isolation region on each buried trench capacitor. A well with the second conductivity is formed in the semiconductor substrate to electrically couple with the diffusion regions. A gate oxide layer is formed on the semiconductor substrate. A conductive gate layer is formed on the gate oxide layer for serving as word lines of an array of DRAM cells. Source/drain regions with the second conductivity are formed in the semiconductor substrate. One source/drain region electrically couples to the buried conductive strap and the other source/drain region is served as a bit line of one DRAM cell. In accordance with the present method, a photolithography and etching process is used to laterally remove away the parts of the collar oxide layer around the inner sidewalls of buried trench capacitors neighboring with each other in a pair of neighboring buried trench capacitors before the dielectric layer of the capacitor is formed. By way of replacing the removed parts of the collar oxide layer with the dielectric layer of the capacitor, for example, a silicon nitride/silicon dioxide (NO) composite layer, and using a strip type pattern along the rows of the buried trench capacitors to define active areas for source/drain regions of access transistors over the buried trench capacitors, additional capacitance is occurred in the peripheral area of the neighboring buried trench capacitors which are not used by a conventional buried trench capacitor. As a result, the capacitance of the buried trench capacitor is increased without either increasing the depth of the buried trench capacitor or thinning down the effective insulator""s thickness of the buried trench capacitor.